A.3 Network Speed

The nodes for the sorting network only need buuers of length 1 and only 1 multiplexer. They have basic costs S A = 1928 and S S = 4104. The network nodes for the Fluent Machine have width 76 for the forward and the backward network. Thus they have basic costs ~ N A = 3104 and ~ N S = 8808. If we reduce the network nodes of design D1 to design an EREW PRAM, we spare the costs for the comparator and reduce the width of the instruction queue by one bit. We then have basic costs N 0 A = 2320 and N 0 S = 6192. In one network cycle the maximum delay path is the following: a packet has to be read out of the input buuer, its address has to be compared with another, it has to be selected by a multiplexer and it has to be stored in the input buuer of the following node. Reading the input buuer takes 3 gate delays, comparing addresses with an i bit carry lookahead adder takes about 2 logi + 2 gate delays, selecting with a multi-plexer takes 2 gate delays, storing in a buuer takes about 3 gate delays. With 32 bit addresses we have 3 + 2 log32 + 2 + 2 + 3 = 20 gate delays. Because we did not count driver delays and setup and hold times we take a network cycle time N = 25 gate delays.